1. Field of the Invention
The present invention relates to a sense amplifier circuit, and in particular to a sense amplifier circuit for a ROM intended to shorten delays in read time.
2. Description of the Prior Art
FIG. 1 shows a circuit diagram of a conventional sense amplifier circuit. A ROM shown in the figure is a mask ROM, and only one column of a storage matrix of semiconductor memory cells is depicted. From the memory cells shown in the figure, one bit datum is read. The sense amplifier circuit comprises a constant-current source 1 electrically connected to a bit line B1 of the column of memory cells 101, 102, - - - , 10n. An electric potential at bit line B1 with respect to the ground potential of the memory cell is detected at a terminal 80 as a sensed signal of the read datum. When no memory cell is addressed, i.e. when all word lines W101, W102, - - - , W10n are in a low level state (hereafter referred to as L level), or when an addressed memory cell, i.e. a memory cell to which a high level gate potential (hereafter referred to as H level) is applied through a word line, is a destroyed memory cell (hereafter referred to as an OFF bit) as shown at memory cell 102, any current path between constant-current supply 1 and the ground is broken on account of the off state of all memory cells. Thus, bit line B1 has an electric potential of V.sub.ss, which is detected at terminal 80 as the sensed signal of H level V.sub.1. When, on the contrary, a retained (not destroyed) memory cell (hereafter referred to as an ON bit) as shown at N MOST (MOS transistor) 101, or 10n is addressed by applying an H-level address signal to the word line, a drain current of a constant current intensity I is allowed to flow in the addressed memory cell. Since the circuit is designed so that the current intensity I is lower than the drain current I.sub.D sat in the saturated region of the I.sub.D -V.sub.D characteristics of the N MOST for the gate potential applied as an address signal, the N MOST operates in the linear region of the I.sub.D -V.sub.D characteristics in order to allow a drain current flow of intensity I. This causes the electric potential of bit line B1 to be L level lower than the pinch-off potential. As a result, a sensed signal of L level V.sub.2 is provided at terminal 80.
In the sense amplifier circuit above, when an OFF bit is read after an ON bit is read, stray capacities present in read-data lines of all memory cells connected to the bit line B1 are charged by the constant current I with a charging time t.sub.1 =C(V.sub.1 -V.sub.2)/I, where C denotes the resultant capacity of the stray capacities. When an ON bit is read after an OFF bit is read, the stray capacities are discharged with the discharging time constant t.sub.2 =C/g.sub.d through the N MOST in the addressed ON bit, wherein g.sub.d denotes the channel conductance of the N MOST.
A problem encountered in the prior art sense amplifier circuit above has been that the rise and fall of each read cycle is delayed by t.sub.1 and t.sub.2, respectively, due to the stray capacities coupled to the bit line. In order to solve the problem, it is necessary to design both I to be high in order to reduce t.sub.1 and g.sub.d of all memory cells to be high in order to reduce t.sub.2. However, meeting the former requirement will cause an increase in power loss of the constant-current source, and meeting the latter requirement will take up a large occupation area of the ROM on an IC substrate in contradiction to the requirement for smaller scaling. It has been considered a further problem that, even when word lines to be addressed belong exclusively to a given group of word lines, and accordingly memory cells to be accessed are limited within those memory cells coupled to the given group of word lines, the stray capacities not only of the memory cells to be accessed but also of all other memory cells contribute to the delay in the read time.